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ds05-11113-1e fujitsu semiconductor data sheet memory buffered 4 m 72 bit synchronous dynamic ram dimm mb8504s072ac-100/-84/-67 200-pin, 2-bank, based on 2 m 8 bit sdrams with pll n description the fujitsu mb8504s072ac is a fully decoded, cmos synchronous dynamic random access memory (sdram) module consisting of eighteen mb81117822a devices which organized as two banks of 1 m 8 bits. this module is possible to minimize the skews of input signals such as clock and address signal by the pll clock driver and register buffers mounted. the mb8504s072ac is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. this module is ideally suited for supercomputers, workstations, high-end pcs, laser printers, high resolution graphic adapters, accelerators, and other applications where a simple interface is needed. n product line & features parameter mb8504s072ac-100 MB8504S072AC-84 mb8504s072ac-67 clock frequency 100 mhz max. 84 mhz max. 67 mhz max. burst mode cycle time 10 ns max. (cl = 4) 15 ns max. (cl = 3) 12 ns max. (cl = 4) 17 ns max. (cl = 3) 15 ns max. (cl = 4) 20 ns max. (cl = 3) ras access time 54.5 ns max. 56.5 ns max. 60.5 ns max. cas access time 24.5 ns max. 26.5 ns max. 30.5 ns max. output valid from clock 9 ns max. (cl = 4) 9.5 ns max. (cl = 3) 9 ns max. (cl = 4) 9.5 ns max. (cl = 3) 9.5 ns max. (cl = 4) 10.5 ns max. (cl = 3) power dissipation burst mode 6253 mw max. 5782 mw max. 5314 mw max. power down mode 572 mw max. 508 mw max. 443 mw max. buffered 200-pin dimm socket type (lead pitch: 1.27 mm) conformed to jedec standard organization: 4,194,304 words 72 bits (ecc) memory: mb81117822a (2 m 8, 2-bank) 18 pcs. 3.3 v 0.3 v supply voltage all input/output lvttl compatible 2048 refresh cycle every 32.8 ms auto and self refresh cke power down mode output enable and input data mask pll clock driver/register buffer/input buffer module size: 1.5 (height) 6.05 (length) 0.16 (thick)
2 mb8504s072ac-100/-84/-67 n package (mds-200p-p07) package and ordering information ?200-pad dimm, order as mb8504s072ac- dg (dg = gold pad) plastic dimm package
3 mb8504s072ac-100/-84/-67 n pin assignments pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v cc 41 v ss 81 dq 15 121 dq 56 161 v ss 2 n.c. 42 a 8 82 dq 14 122 v cc 162 dq 31 3 n.c. 43 a 9 83 v ss 123 dq 55 163 dq 30 4in 44v cc 84 dq 13 124 dq 54 164 v cc 5 out 45 cke 1 85 dq 12 125 v ss 165 dq 29 6id 0 46 cke 0 86 v cc 126 dq 53 166 dq 28 7id 1 47 v ss 87 dq 7 127 dq 52 167 v ss 8v ss 48 cas 88 dq 6 128 v cc 168 dq 23 9dq 67 49 n.c. 89 v ss 129 dq 47 169 dq 22 10 dq 66 50 v cc 90 dq 5 130 dq 46 170 v cc 11 v cc 51 v ss 91 dq 4 131 v ss 171 dq 21 12 dq 65 52 ras 92 v cc 132 dq 45 172 dq 20 13 dq 64 53 v ss 93 pde 133 dq 44 173 v ss 14 v ss 54 n.c. 94 pd 1 134 v cc 174 n.c. 15 dq 63 55 n.c. 95 pd 2 135 dq 39 175 n.c. 16 dq 62 56 v cc 96 pd 3 136 dq 38 176 v cc 17 n.c. 57 a 0 97 pd 4 137 v ss 177 n.c. 18 dq 61 58 a 1 98 n.c. 138 dq 37 178 v ss 19 dq 60 59 v ss 99 n.c. 139 dq 36 179 v ss 20 v cc 60 dq 35 100 v ss 140 v cc 180 n.c. 21 n.c. 61 dq 34 101 n.c. 141 a 6 181 n.c. 22 n.c. 62 v cc 102 n.c. 142 a 7 182 v cc 23 v ss 63 dq 33 103 v ss 143 v ss 183 dq 11 24 n.c. 64 dq 32 104 n.c. 144 a 11 184 dq 10 25 n.c. 65 v ss 105 n.c. 145 n.c. 185 v ss 26 v cc 66 dq 27 106 n.c. 146 v cc 186 dq 9 27 dq 51 67 dq 26 107 id 2 147 dqm 187 dq 8 28 dq 50 68 v cc 108 dq 71 148 we 188 v cc 29 v ss 69 dq 25 109 dq 70 149 v ss 189 dq 3 30 dq 49 70 dq 24 110 v ss 150 n.c. 190 dq 2 31 dq 48 71 v ss 111 dq 69 151 clk 191 v ss 32 v cc 72 dq 19 112 dq 68 152 v cc 192 dq 1 33 dq 43 73 dq 18 113 v cc 153 cs 1 193 dq 0 34 dq 42 74 v cc 114 n.c. 154 cs 0 194 pd 5 35 v ss 75 dq 17 115 v ss 155 v ss 195 pd 6 36 dq 41 76 dq 16 116 n.c. 156 n.c. 196 pd 7 37 dq 40 77 v ss 117 dq 59 157 a 10 197 pd 8 38 v cc 78 n.c. 118 dq 58 158 v cc 198 v cc 39 a 4 79 n.c. 119 v ss 159 a 2 199 n.c. 40 a 5 80 v cc 120 dq 57 160 a 3 200 n.c.
4 mb8504s072ac-100/-84/-67 n pin description symbol i/o function symbol i/o function a 0 to a 11 i address input dq 0 to dq 71 i/o data input/data output ras i row address strobe v cc power supply (+3.3 v) cas i column address strobe v ss ground (0 v) we i write enable n.c. no connection dqm i data (dq) mask pd 1 to pd 8 o presence detect clk i clock input id 0 to id 2 o id bit cke 0 , cke 1 i clock enable pde i precence detect enable cs 0 , cs 1 i chip select top view chip 0 1 100 plane 0 38.1 mm 153.7 mm (mds-200p-p07) chip 1 chip 2 chip 3 chip 4 chip 5 chip 6 chip 7 chip 8 pll alvc chip 9 101 200 plane 1 chip 10 chip 11 chip 12 chip 13 chip 14 chip 15 chip 16 chip 17
5 mb8504s072ac-100/-84/-67 n presence detect(pd)/id definition symbol mb8504s072ac -100 mb8504s072ac -84 mb8504s072ac -67 description of pd/id pd 1 hhh module configuration, sdram organization, and addressing; module con?uration: 4 m 72 mounted sdram con?uration: 2 m 8 sdram address (row/column): 12/9 pd 2 lll pd 3 lll pd 4 lll pd 5 hlh module speed; 10 ns: pd 5 = h, pd 6 = l 12 ns: pd 5 = l, pd 6 = h 15 ns: pd 5 = h, pd 6 = h pd 6 lhh pd 7 h h h buffering; buffered: pd 7 = h pd 8 h h h byte write; word: pd 8 = h id 0 open open open column to column command interval; 1 clock: id 0 = open id 1 v ss v ss v ss read precharge position; no early ras: id 1 = v ss id 2 v ss v ss v ss power; normal: id 2 = v ss
6 mb8504s072ac-100/-84/-67 plane 1 plane 0 ras cas we dqm a 0 to a 11 cs 0 cke 0 cs 1 cke 1 chip 18 fbin clkin cdc2586 pll clock driver clk sn74lvc244 chip 20 in out id 0 id 1 id 2 clk ras cas we dqm a 0 to a 11 cs cke chip 19 y pde block diagram 10 w v cc or v ss pd 1 to pd 8 dq 71 dq 70 dq 69 dq 68 dq 67 dq 66 dq 65 dq 64 dq 63 dq 62 dq 61 dq 60 dq 59 dq 58 dq 57 dq 56 dq 47 dq 46 dq 45 dq 44 dq 43 dq 42 dq 41 dq 40 dq 55 dq 54 dq 53 dq 52 dq 51 dq 50 dq 49 dq 48 dq 33 dq 32 dq 29 dq 28 dq 27 dq 26 dq 23 dq 22 dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 39 dq 38 dq 37 dq 36 dq 35 dq 34 dq 31 dq 30 dq 25 dq 24 dq 21 dq 20 dq 19 dq 18 dq 17 dq 16 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 2clk 1clk 2 mw 8 chip 0 2 mw 8 chip 1 2 mw 8 chip 2 2 mw 8 chip 3 2 mw 8 chip 9 2 mw 8 chip 10 2 mw 8 chip 11 2 mw 8 chip 12 2 mw 8 chip 4 2 mw 8 chip 13 2 mw 8 chip 5 2 mw 8 chip 14 2 mw 8 chip 6 2 mw 8 chip 15 2 mw 8 chip 7 2 mw 8 chip 16 2 mw 8 chip 8 2 mw 8 chip 17 clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke clk ras cas we dqm a 0 to a 11 cs cke
7 mb8504s072ac-100/-84/-67 n absolute maximum ratings (see warning) * : voltages referenced to v ss (= 0 v) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions *1. voltages referenced to v ss (= 0 v) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. n capacitance (v cc = +3.3 v, f = 1 mhz, t a = +25 c) parameter symbol value unit min. max. supply voltage* v cc ?.5 +4.6 v input voltage* v in ?.5 +4.6 v output voltage* v out ?.5 +4.6 v storage temperature t stg ?5 +125 c power dissipation p d ?2w output current (d.c.) i out ?0 +50 ma parameter notes symbol value unit min. typ. max. supply voltage *1 v cc 3.0 3.3 3.6 v v ss 000v input high voltage, all inputs *1 v ih 2.0 v cc +0.5 v input low voltage, all inputs *1 v il ?.5 0.8 v ambient temperature t a 0 +70 c parameter symbol value unit min. max. input capacitance a 0 to a 11 c in1 ?0pf ras , cas , we c in2 ?0pf cs 0 , cs 1 c in3 ?0pf cke 0 , cke 1 c in4 ?0pf clk c in5 ?0pf dqm c in6 ?0pf input/output capacitance dq 0 to dq 71 c dq ?3pf
8 mb8504s072ac-100/-84/-67 n dc characteristics (at recommended operating conditions unless otherwise noted.) parameter notes symbol condition value unit min. max. operating current (average power supply current) *2 mb8504s072ac-100 i cc1s no burst; t ck = min t rc = min one bank active 1190 ma MB8504S072AC-84 1120 ma mb8504s072ac-67 1051 ma mb8504s072ac-100 i cc1d no burst; t ck = min t rc = min all banks active 1640 ma MB8504S072AC-84 1518 ma mb8504s072ac-67 1396 ma precharge standby current (power supply current) *2 mb8504s072ac-100 i cc2p cke = v il , t ck = min all banks idle 159 ma MB8504S072AC-84 141 ma mb8504s072ac-67 123 ma mb8504s072ac-100 i cc2n cke = v ih , t ck = min all banks idle 636 ma MB8504S072AC-84 621 ma mb8504s072ac-67 607 ma active standby current (power supply current) *2 mb8504s072ac-100 i cc3p cke = v il , t ck = min any bank active 636 ma MB8504S072AC-84 621 ma mb8504s072ac-67 607 ma mb8504s072ac-100 i cc3n cke = v ih , t ck = min any bank active 816 ma MB8504S072AC-84 801 ma mb8504s072ac-67 787 ma burst mode current (average power supply current) *2 mb8504s072ac-100 i cc4 t ck = min 1737 ma MB8504S072AC-84 1606 ma mb8504s072ac-67 1476 ma auto-refresh current (average power supply current) *2 mb8504s072ac-100 i cc5 auto refresh t ck = min t rc = min t rrd = min 1377 ma MB8504S072AC-84 1269 ma mb8504s072ac-67 1161 ma self-refresh current (average power supply current) mb8504s072ac-100 i cc6 t ck = v il 384 ma MB8504S072AC-84 369 ma mb8504s072ac-67 355 ma input leakage current (all inputs except dq) i i (l) v in = 0 v ?0 10 m a v in = v cc ?0 10 input hold current (all inputs except clk, pde , dq) i i (hold) v in = 0.8 v 75 m a v in = 2 v ?5 output leakage current (all dq) i o (l) output is disabled (hi-z) 0 v v out v cc 3.0 v v cc 3.6 v ?0 10 m a lvttl output high voltage *1 v oh i oh = ?.0 ma 2.4 v lvttl output low voltage *1 v ol i ol = +2.0 ma 0.4 v
9 mb8504s072ac-100/-84/-67 notes: *1. voltages referenced to v ss (= 0 v) *2. i cc depends on the output termination, load conditions, clock cycle rate and signal clock rate. the speci?d values are obtained with the output open and no termination register. *3. an initial pause (desl on nop) of 200 m s is required after power-on followed by a minimum of eight auto-refresh cycles. *4. values except i cc2p are for when one side of the double-sided module is in standby mode and the other side has two banks active in burst mode.
10 mb8504s072ac-100/-84/-67 n ac characteristics (1) base characteristics (at recommended operating conditions unless otherwise noted.) no. parameter notes symbol mb8504s072ac -100 mb8504s072ac -84 mb8504s072ac -67 unit min. max. min. max. min. max. 1 clock period cl = 4 t ck 10 20 12 20 15 20 ns cl = 3 152017202020ns 2 clock high time t ch 44.8?ns 3 clock low time t cl 44.8?ns 4cs set up time t sc 3.4 3.4 3.4 ns 5cs hold time t hc 1??ns 6 input set up time t si 3.4 3.4 3.4 ns 7 input hold time t hi 1??ns 8 data input set up time t sid 3.5 3.5 3.5 ns 9 data input hold time t hid 1.5 1.5 1.5 ns 10 output valid from clock (t clk = min) *1, *2 cl = 4 t ac ??9.5 ns cl = 3 9.5 9.5 10.5 11 output in low-z t olz 2.5 2.5 2.5 ns 12 output in high-z *3 t ohz 2.5 2.5 2.5 ns 13 output hold time t oh 2.5 2.5 2.5 ns 14 time between refresh t ref 32.8 32.8 32.8 ms 15 transition time t t 0.5 2 0.5 2 0.5 2 ns 16 power down exit time t pde 3.5 4.5 5.5 ns
11 mb8504s072ac-100/-84/-67 (2) base values for clock count/latency (3) clock count formula (*8) (4) latency (the latency values on these parameters are ?ed regardless of clock period.) no. parameter notes symbol mb8504s072ac -100 mb8504s072ac -84 mb8504s072ac -67 unit min. max. min. max. min.. max. 1 ras cycle time *4 t rc 90 100 110 ns 2 ras access time *5 t rac 54.5 56.5 60.5 ns 3 cas access time *6, *9 t cac 24.5 26.5 30.5 ns 4 ras precharge time t rp 30?5?0ns 5 ras active time t ras 60 100000 65 100000 70 100000 ns 6 ras to cas delay time *7 t rcd 30?0?0ns 7 write recovery time t wr 10?2?5ns 8 write precharge time t rwl 10?2?5ns 9 ras to ras bank active delay time t rrd 30?0?0ns no. parameter symbol mb8504s072ac -100 mb8504s072ac -84 mb8504s072ac -67 unit 1 cke to clock disable i cke 2 2 2 cycle 2 dqm to output in high-z i dqz 3 3 3 cycle 3 dqm to input data delay i dqd 1 1 1 cycle 4 last output to write command delay i owd 1 1 1 cycle 5 write command to input data delay i dwd 1 1 1 cycle 6 precharge to output in high-z delay cl = 4 i roh 4 4 4 cycle cl = 3 3 3 3 cycle 7 mode register access to bank active (min) i mrd 2 2 2 cycle 8 cas to cas delay (min) i ccd 1 1 1 cycle 9 cas bank delay (min) i cbd 1 1 1 cycle clock 3 base value clock period (round off a whole number)
12 mb8504s072ac-100/-84/-67 notes: *1. assumes t rcd and t cac are satis?d. *2. t ac also speci?s the access time at burst mode except for ?st access. *3. speci?d where output buffer is no longer driven. *4. actual clock count of t rc (i rc ) will be sum of clock count of t ras (i ras ) and t rp (i rp ). *5. t rac is a reference value. maximum value is obtained from the sum of t rcd (min) and t cac (max). *6. assumes t rac and t ac are satis?d. *7. operation within the t rcd (min) ensures that t rac can be met; if t rcd is greater than the speci?d t rcd (min), access time is determined by t cac and t ac . *8. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *9. the i cac (cas latency: cl) is programmed by the mode register. *10. an initial pause (desl on nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. *11. 1.4 v or v ref is the reference level for measuring timing of signals. transition times are measured between v ih (min) and v il (max). *12. ac characteristics assume t t = 1 ns and 30 pf of capacitive load. *source: see mb81117822a data sheet for details on the electricals.
13 mb8504s072ac-100/-84/-67 n ac operating test condition (example of ac test load circuit) i/o z = 50 w 50 w 1.4 v 30 pf
14 mb8504s072ac-100/-84/-67 n package dimension 200-pad plastic dual in-line type module (case no.: mds-200p-p07) c 1996 fujitsu limited m200007sc-1-1 3.00(.118)min. 153.700.13 38.100.13 (1.500.005) 45.720.13 (1.800.005) 1.00(.039)typ. 2.54(.100)typ. 0.25(.010)max. 1.27 +0.10 ?0.08 +.004 ?.003 .050 1 4.000.10 (.157.004) 100 3.000.08 (.118.002) "b" 19.050.05 (.750.002) 1.270.03 (.050.001) 38.100.13 (1.500.005) 77.470.05 (3.050.002) 26.670.05 (1.050.002) resistor mounting area. 3.00(.118) 3.25(.128) 6.350.13 (.250.005) 2.000.10 (.079.004) 200 101 ? 3.000.05 (? .118.002) r1.000.05 (r.039.002) r2.000.05 (r.079.002) (6.051.005) 10.000.13 (.394.005) pin no.1 index "a" details of "a" part details of "b" part 146.400.10 (5.764.004) (5.350.005) 135.890.13 4.00(.157)min. 4.06(.160)max. 3.175(.125)typ. dimension in mm (inches)
15 mb8504s072ac-100/-84/-67 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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